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1 ltc2847 sn2847 2847fs applicatio s u descriptio u features typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. complete dte or dce multiprotocol serial interface with db-25 connector n data networking n csu and dsu n data routers n software-selectable transceiver supports: rs232, rs449, eia530, eia530-a, v.35, v.36, x.21 n operates from single 5v supply n separate supply pin for digital interface works down to 3v n on-chip cable termination n complete dte or dce port with ltc2845 n available in 38-pin 5mm 7mm qfn package the ltc ? 2847 is a 3-driver/3-receiver multiprotocol trans- ceiver with on-chip cable termination. when combined with the ltc2845, this chip set forms a complete software- selectable dte or dce interface port that supports the rs232, rs449, eia530, eia530-a, v.35, v.36 and x.21 protocols. all necessary cable termination is provided inside the ltc2847. the v cc supplies the drivers, the receivers and an internal charge pump that requires only five space-saving surface mounted capacitors. the v in supply drives the digital inter- face circuitry including the receiver output drivers. it can be tied to v cc or be powered off a lower supply (down to 3v) to interface with low voltage asics. the ltc2847 is available in a 0.8mm tall, 5mm 7mm qfn package. software-selectable multiprotocol transceiver with termination and 3.3v digital interface d2 d1 ltc2845 rts dtr dsr dcd cts d3 r2 r1 r4 r3 ltc2847 ri ll tm rl txd scte txc rxc rxd 2 14 24 11 15 12 17 9 3 1 4 19 20 823 10 5 13 6 22 18 25 21 716 2847 ta01 d1 scte b scte a (113) txd b txd a (103) rxc a (115) rxc b rxd a (104) rxd b rts a (105) rts b dtr a (108) dtr b ll a (141) tm (142) rl (140) sg (102) shield (101) db-25 connector txc a (114) dcd a (109) dcd b dsr a (107) dsr b d4 r5 d5 d2 d3 r1 r2 r3 txc b t t t t t cts a (106) cts b ri (125) * *optional
2 ltc2847 sn2847 2847fs order part number (note 1) v cc voltage.............................................. C 0.3v to 6.5v v in voltage .............................................. C 0.3v to 6.5v input voltage transmitters ........................... C 0.3v to (v cc + 0.3v) receivers ............................................... C 18v to 18v logic pins .............................. C 0.3v to (v cc + 0.3v) output voltage transmitters ................. (v ee C 0.3v) to (v dd + 0.3v) receivers ................................. C 0.3v to (v in + 0.3v) v ee ........................................................ C 10v to 0.3v v dd ....................................................... C 0.3v to 10v short-circuit duration transmitter output ..................................... indefinite receiver output .......................................... indefinite v ee .................................................................. 30 sec operating temperature range ltc2847c ............................................... 0 c to 70 c ltc2847i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c ltc2847cuhf ltc2847iuhf absolute axi u rati gs w ww u package/order i for atio uu w the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v in = 3.3v, unless otherwise noted (notes 2, 3) electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges. uhf part marking 2847 2847i 13 14 15 16 top view uhf package 38-lead (7mm 5mm) plastic qfn underside metal internally connected to v ee (pcb connection optional) 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 23 22 21 20 9 10 11 12 nc v dd nc v cc d1 d2 d3 r1 r2 r3 m0 m1 v in m2 dce/dte r3 b r3 a nc nc c1 + c1 v ee c2 + c2 v ee v ee gnd gnd d1 a d1 b d2 a d2 b d3/r1 a d3/r1 b nc nc r2 a r2 b t jmax = 125 c, q ja = 34 c/w symbol parameter conditions min typ max units supplies i cc v cc supply current (dce mode, rs530, rs530-a, x.21 modes, no load 14 ma all digital pins = gnd or v in ) rs530, rs530-a, x.21 modes, full load l 100 130 ma v.35 mode l 126 170 ma v.28 mode, no load 20 ma v.28 mode, full load l 35 75 ma no-cable mode l 300 900 m a i vin v in supply current all modes except no-cable mode 405 m a (dce mode, all digital pins = gnd or v in ) p d internal power dissipation (dce mode) rs530, rs530-a, x.21 modes, full load 410 mw v.35 mode, full load 625 mw v.28 mode, full load 150 mw v + positive charge pump output voltage v.11 or v.28 mode, no load l 8 9.3 v v.35 mode l 7 8.0 v v.28 mode, with load l 8 8.7 v v.28 mode, with load, i dd = 10ma 6.5 v
3 ltc2847 sn2847 2847fs the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v in = 3.3v, unless otherwise noted (notes 2, 3) electrical characteristics symbol parameter conditions min typ max units v C negative charge pump output voltage v.28 mode, no load C 9.6 v v.28 mode, full load l C 7.5 C 8.5 v v.35 mode l C 5.5 C 6.5 v rs530, rs530-a, x.21 modes, full load l C 4.5 C 6.0 v f osc charge pump oscillator frequency 500 khz t r charge pump rise time no-cable mode/power-off to normal operation 2 ms logic inputs and outputs v ih logic input high voltage d1, d2, d3, m0, m1, m2, dce/dte l 2.0 v v il logic input low voltage d1, d2, d3, m0, m1, m2, dce/dte l 0.8 v i in logic input current d1, d2, d3 l 10 m a m0, m1, m2, dce/dte = gnd l C 30 C 75 C 120 m a m0, m1, m2, dce/dte = v in l 10 m a v oh output high voltage i o = C 3ma l 2.7 3 v v ol output low voltage i o = 1.6ma l 0.2 0.4 v i osr output short-circuit current 0v v o v in l 50 ma i ozr three-state output current m0 = m1 = m2 = v in , v o = gnd l C30 C85 C160 m a m0 = m1 = m2 = v in , v o = v in l 10 m a v.11 driver v odo open circuit differential output voltage r l = 1.95k (figure 1) l 5v v odl loaded differential output voltage r l = 50 w (figure 1) 0.5v odo 0.67v odo v r l = 50 w (figure 1) l 2v d v od change in magnitude of differential r l = 50 w (figure 1) l 0.2 v output voltage v oc common mode output voltage r l = 50 w (figure 1) l 3v d v oc change in magnitude of common mode r l = 50 w (figure 1) l 0.2 v output voltage i ss short-circuit current v out = gnd 150 ma i oz output leakage current ? v a ? and ? v b ? 0.25v, power off or l 1 100 m a no-cable mode or driver disabled t r , t f rise or fall time (figures 2, 13) l 21525 ns t plh input to output rising (figures 2, 13) l 15 40 65 ns t phl input to output falling (figures 2, 13) l 15 40 65 ns d t input to output difference, ? t plh C t phl ? (figures 2, 13) l 0312 ns t skew output to output skew (figures 2, 13) 3 ns
4 ltc2847 sn2847 2847fs the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v in = 3.3v, unless otherwise noted (notes 2, 3) electrical characteristics symbol parameter conditions min typ max units v.11 receiver v th input threshold voltage C 7v v cm 7v l C 0.2 0.2 v d v th input hysteresis C 7v v cm 7v l 15 40 mv r in input impedance C7v v cm 7v (figure 3) l 100 103 w t r , t f rise or fall time c l = 50pf (figures 4, 14) 15 ns t plh input to output rising c l = 50pf (figures 4, 14) l 50 90 ns t phl input to output falling c l = 50pf (figures 4, 14) l 50 90 ns d t input to output difference, ? t plh C t phl ? c l = 50pf (figures 4, 14) l 0425 ns v.35 driver v od differential output voltage open circuit, r l = 1.95k (figure 5) l 1.2 v with load, C 4v v cm 4v (figure 6) 0.44 0.55 0.66 v v oa , v ob single-ended output voltage open circuit, r l = 1.95k (figure 5) l 1.2 v v oc transmitter output offset r l = 50 w (figure 5) l 0.6 v i oh transmitter output high current v a , v b = 0v l C9 C11 C13 ma i ol transmitter output low current v a , v b = 0v l 91113 ma i oz transmitter output leakage current ? v a ? and ? v b ? 0.25v l 1 100 m a r od transmitter differential mode impedance l 50 100 150 w r oc transmitter common mode impedance C 2v v cm 2v (figure 7) 135 150 165 w t r , t f rise or fall time (figures 8, 13) 5 ns t plh input to output (figures 8, 13) l 15 35 65 ns t phl input to output (figures 8, 13) l 15 35 65 ns d t input to output difference, ? t plh C t phl ? (figures 8, 13) l 016 ns t skew output to output skew (figures 8, 13) 4 ns v.35 receiver v th differential receiver input threshold voltage C 2v v cm 2v (figure 9) l C 0.2 0.2 v d v th receiver input hysteresis C 2v v cm 2v (figure 9) l 15 40 mv r id receiver differential mode impedance C 2v v cm 2v l 90 103 110 w r ic receiver common mode impedance C 2v v cm 2v (figure 10) 135 150 165 w t r , t f rise or fall time c l = 50pf (figures 4, 14) 15 ns t plh input to output c l = 50pf (figures 4, 14) l 50 90 ns t phl input to output c l = 50pf (figures 4, 14) l 50 90 ns d t input to output difference, ? t plh C t phl ? c l = 50pf (figures 4, 14) l 0425 ns v.28 driver v o output voltage open circuit l 10 v r l = 3k (figure 11) l 5 8.5 v i ss short-circuit current v out = gnd l 150 ma r oz power-off resistance C 2v < v o < 2v, power off l 300 w or no-cable mode sr slew rate r l = 7k, c l = 0 (figures 11, 15) l 430v/ m s t plh input to output r l = 3k, c l = 2500pf (figures 11, 15) l 1.5 2.5 m s t phl input to output r l = 3k, c l = 2500pf (figures 11, 15) l 1.5 2.5 m s
5 ltc2847 sn2847 2847fs the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v in = 3.3v, unless otherwise noted (notes 2, 3) electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all currents into device pins are positive; all currents out of device are negative. all voltages are referenced to device ground unless otherwise specified. note 3: all typicals are given for v cc = 5v, v in = 3.3v, c vcc = c vin = 10 m f, c vdd = 1 m f, c vee = 3.3 m f and t a = 25 c. symbol parameter conditions min typ max units v.28 receiver v thl input low threshold voltage (figure 12) l 0.8 v v tlh input high threshold voltage (figure 12) l 2v d v th receiver input hysteresis (figure 12) l 0 0.05 0.3 v r in receiver input impedance C 15v v a 15v l 357 k w t r , t f rise or fall time c l = 50pf (figures 12, 16) 15 ns t plh input to output c l = 50pf (figures 12, 16) l 60 300 ns t phl input to output c l = 50pf (figures 12, 16) l 160 300 ns typical perfor a ce characteristics uw v.11 mode i cc vs data rate data rate (kbd) 10 i cc (ma) 120 130 140 2846 g04 110 100 90 100 1000 150 160 170 10000 t a = 25 c data rate (kbd) 10 120 i cc (ma) 125 130 135 140 150 100 1000 2846 g05 10000 145 t a = 25 c data rate (kbd) 10 30 i cc (ma) 35 40 45 50 60 20 40 60 80 100 2846 g06 55 t a = 25 c v.35 mode i cc vs data rate v.28 mode i cc vs data rate v.11 mode i cc vs temperature v.35 mode i cc vs temperature v.28 mode i cc vs temperature temperature ( c) ?0 i cc (ma) 100 105 110 20 60 2846 g07 95 90 ?0 0 40 80 100 85 80 temperature ( c) ?0 123.0 i cc (ma) 123.5 124.5 125.0 125.5 128.0 126.5 0 40 60 2846 g08 124.0 127.0 127.5 126.0 ?0 20 80 100 temperature ( c) ?0 i cc (ma) 37.0 20 3846 g09 35.5 34.5 ?0 0 40 34.0 33.5 37.5 36.5 36.0 35.0 60 80 100
6 ltc2847 sn2847 2847fs uu u pi fu ctio s nc (pins 1,3,18,19,22,23): no connect. v dd (pin 2): generated positive supply voltage for v.28. connect a 1 m f capacitor to ground. v cc (pin 4): input supply pin. input supply to charge pump and transceiver. 4.75v v cc 5.25v. connect a 1 m f capacitor to gnd. d1 (pin 5): ttl level driver 1 input. d2 (pin 6): ttl level driver 2 input. d3 (pin 7): ttl level driver 3 input. r1 (pin 8): cmos level receiver 1 output with pull-up to v in when three-stated. r2 (pin 9): cmos level receiver 2 output with pull-up to v in when three-stated. r3 (pin 10): cmos level receiver 3 output with pull-up to v in when three-stated. m0 (pin 11): ttl level mode select input 0 with pull-up to v in . see table 1. m1 (pin 12): ttl level mode select input 1 with pull-up to v in . see table 1. v in (pin 13): input supply pin. input supply to digital interface including receiver output drivers. 3v v in 5.25v. connect to v cc (pin 4) or to separate supply for lower receiver output swing. connect a 1 m f capacitor to gnd. m2 (pin 14): ttl level mode select input 2 with pull-up to v in . see table 1. dce/dte (pin 15): ttl level mode select input with pull-up to v in . see table 1. r3 b (pin 16): receiver 3 noninverting input. r3 a (pin 17): receiver 3 inverting input. r2 b (pin 20): receiver 2 noninverting input. r2 a (pin 21): receiver 2 inverting input. d3/r1 b (pin 24): receiver 1 noninverting input and driver 3 noninverting output. d3/r1 a (pin 25): receiver 1 inverting input and driver 3 inverting output. d2 b (pin 26): driver 2 noninverting output. d2 a (pin 27): driver 2 inverting output. d1 b (pin 28): driver 1 noninverting output. d1 a (pin 29): driver 1 inverting output. gnd (pins 30,31): transceiver ground. v ee (pins 32,33,36): generated negative supply voltage. connect a 3.3 m f capacitor to gnd. exposed pad can also be connected to v ee . c2 C (pin 34): capacitor c2 negative terminal. connect a 1 m f capacitor between c2 + and c2 C . c2 + (pin 35): capacitor c2 positive terminal. connect a 1 m f capacitor between c2 + and c2 C . c1 C (pin 37): capacitor c1 negative terminal. connect a 1 m f capacitor between c1 + and c1 C . c1 + (pin 38): capacitor c1 positive terminal. connect a 1 m f capacitor between c1 + and c1 C .
7 ltc2847 sn2847 2847fs block diagra w c1 c1 + v dd v cc c1 c1 + v dd c2 + c2 v ee gnd c2 + c2 v ee gnd charge pump d1 d1 a 50 125 50 s1 s2 d1 b d1 d2 d2 a 50 125 50 s1 s2 d2 b s3 s2 20k 20k 20k 20k 125 s2 s3 125 10k 6k s1 51.5 d3/r1 a d3/r1 b 51.5 10k 10k 10k 51.5 r2 a r2 b 51.5 d2 d3 dce/dte r1 d3 r1 r2 r2 6k 20k 20k mode selection logic s2 s3 125 10k 10k 51.5 r3 a r3 b 2847 bd 51.5 r3 r3 6k 35 37 38 2 4 5 6 7 15 8 9 10 v in 13 m0 11 m1 12 m2 14 34 36 33 32 31 30 29 28 27 26 25 24 21 20 17 16 v cc
8 ltc2847 sn2847 2847fs figure 1. v.11 driver dc test circuit figure 2. v.11 driver ac test circuit figure 4. v.11, v.35 receiver ac test circuit figure 3. input impedance test circuit figure 5. v.35 driver open-circuit test figure 6. v.35 driver test circuit figure 7. v.35 driver common mode impedance test circuit figure 8. v.35 driver ac test circuit figure 9. v.35 receiver dc test circuit figure 10. receiver common mode impedance test circuit figure 11. v.28 driver test circuit figure 12. v.28 receiver test circuit test circuits 2847 f01 v od v oc r l r l a b d a b d 2847 f02 r l 100 w c l 100pf c l 100pf r 2847 f03 v cm = 7v b i b a + i a 2(v b ?v a ) i b ?i a r in = a b 2847 f04 r c l 2847 f05 v od v oc r l 50 v ob v oa 125 50 r l 2847 f06 50 v ob v oa 125 125 50 50 50 v cm 2847 f07 50 125 50 v cm = 2v + 2847 f08 50 50 125 125 50 50 2847 f09 v th v cm + + 2847 f10 51.5 125 51.5 v cm = 2v + a d 2847 f11 r l c l r a 2847 f12 c l v a
9 ltc2847 sn2847 2847fs mode name m2 m1 m0 dce/ d1,2 d3 d1 d2 d3 r1 r2 r3 r1 r2,r3 v dd v ee dte (note 2) (note 2) (note 2) (note 3) (note 3) (note 4) (note 5) ababababab ab not used (default v.11) 0 0 0 0 ttl x v.11 v.11 v.11 v.11 z z v.11 v.11 v.11 v.11 v.11 v.11 cmos cmos 9.3v C6v rs530a 0 0 1 0 ttl x v.11 v.11 v.11 v.11 z z v.11 v.11 v.11 v.11 v.11 v.11 cmos cmos 9.3v C6v rs530 0 1 0 0 ttl x v.11 v.11 v.11 v.11 z z v.11 v.11 v.11 v.11 v.11 v.11 cmos cmos 9.3v C6v x.21 0 1 1 0 ttl x v.11 v.11 v.11 v.11 z z v.11 v.11 v.11 v.11 v.11 v.11 cmos cmos 9.3v C6v v.35 1 0 0 0 ttl x v.35 v.35 v.35 v.35 z z v.35 v.35 v.35 v.35 v.35 v.35 cmos cmos 8v C6.5v rs449/v.36 1 0 1 0 ttl x v.11 v.11 v.11 v.11 z z v.11 v.11 v.11 v.11 v.11 v.11 cmos cmos 9.3v C6v v.28/rs232 1 1 0 0 ttl x v.28 z v.28 z z z v.28 30k v.28 30k v.28 30k cmos cmos 8.7v C8.5v no cable 1 1 1 0 x x zzzzzz30k30k30k30k30k30kz z 4.7v 0.3v not used (default v.11) 0 0 0 1 ttl ttl v.11 v.11 v.11 v.11 v.11 v.11 30k 30k v.11 v.11 v.11 v.11 z cmos 9.3v C6v rs530a 0 0 1 1 ttl ttl v.11 v.11 v.11 v.11 v.11 v.11 30k 30k v.11 v.11 v.11 v.11 z cmos 9.3v C6v rs530 0 1 0 1 ttl ttl v.11 v.11 v.11 v.11 v.11 v.11 30k 30k v.11 v.11 v.11 v.11 z cmos 9.3v C6v x.21 0 1 1 1 ttl ttl v.11 v.11 v.11 v.11 v.11 v.11 30k 30k v.11 v.11 v.11 v.11 z cmos 9.3v C6v v.35 1 0 0 1 ttl ttl v.35 v.35 v.35 v.35 v.35 v.35 30k 30k v.35 v.35 v.35 v.35 z cmos 8v C6.5v rs449/v.36 1 0 1 1 ttl ttl v.11 v.11 v.11 v.11 v.11 v.11 30k 30k v.11 v.11 v.11 v.11 z cmos 9.3v C6v v.28/rs232 1 1 0 1 ttl ttl v.28 z v.28 z v.28 z 30k 30k v.28 30k v.28 30k z cmos 8.7v C8.5v no cable 1 1 1 1 x x zzzzzz30k30k30k30k30k30kz z 4.7v 0.3v switchi g ti e wavefor s uw w figure 14. v.11, v.35 receiver propagation delays figure 13. v.11, v.35 driver propagation delays ode selectio w u table 1 3v 1.5v 1.5v 50% 10% 90% t plh t r 0v v o v o ? o d b ?a a b t phl t skew t skew 2847 f13 1/2 v o f = 1mhz : t r 10ns : t f 10ns 50% 10% 90% t f v od2 ? od2 0v 1.65v 0v 1.65v t plh v oh v ol b ?a r t phl 2847 f14 f = 1mhz : t r 10ns : t f 10ns input output note 1: driver inputs are ttl level compatible. note 2: unused receiver inputs are terminated with 30k to ground. in addition, r2 and r3 are always terminated by a 103 w differential impedence (see block diagram on page 7). note 3: receiver outputs are cmos level compatible and have a weak pull up to v in when z. note 4: v dd values shown are typical values for v cc = 5v, v in = 3.3v and t a = 25 c with ltc2847 under full load for each mode. note 5: v ee values shown are typical values for v cc = 5v, v in = 3.3v and t a = 25 c with ltc2847 under full load for each mode. (note 1) (note 1)
10 ltc2847 sn2847 2847fs figure 15. v.28 driver propagation delays figure 16. v.28 receiver propagation delays switchi g ti e wavefor s uw w applicatio s i for atio wu uu 3v 0v 1.5v 0v ?v 3v 1.5v 0v 3v ?v t phl t f v o ? o d a t plh t r 2847 f15 sr = 6v t f sr = 6v t r v ih v il 1.5v 1.65v 1.5v 1.65v t phl v oh v ol a r t plh 2847 f16 overview the ltc2847 consists of a charge pump and a 3-driver/ 3-receiver transceiver. the 5v v cc input powers the charge pump and transceiver. the charge pump generates the v dd and v ee supplies. the ltc2847s v dd and v ee supplies can be used to power a companion chip like the ltc2845. the v in input powers the digital interface in- cluding the receiver output drivers. having a separate pin to power the digital interface allows the flexibility of controlling the receiver output swing to interface with 5v or 3.3v logic. the ltc2847 and ltc2845 form a complete software- selectable dte or dce interface port that supports the rs232, rs449, eia530, eia530-a, v.35, v.36 and x.21 protocols. cable termination is provided on-chip, elimi- nating the need for discrete termination designs. a complete dce-to-dte interface operating in eia530 mode is shown in figure 17. the ltc2847 half of each port is used to generate and appropriately terminate the clock and data signals. the ltc2845 is used to generate the control signals along with ll (local loopback), rl (remote loop-back), tm (test mode) and ri (ring indicate). mode selection the interface protocol is selected using the mode select pins m0, m1 and m2 (see table 1). for example, if the port is configured as a v.35 interface, the mode selection pins should be m2 = 1, m1 = 0, m0 = 0. for the control signals, the drivers and receivers will operate in v.28 (rs232) electrical mode. for the clock and data signals, the drivers and receivers will operate in v.35 electrical mode. the dce/dte pin will configure the port for dce mode when high, and dte when low. the interface protocol may be selected simply by plugging the appropriate interface cable into the connector. the mode pins are routed to the connector and are left uncon- nected (1) or wired to ground (0) in the cable as shown in figure 18. the internal pull-up current sources will ensure a binary 1 when a pin is left unconnected. the mode selection may also be accomplished by using jumpers to connect the mode pins to ground or v in .
11 ltc2847 sn2847 2847fs figure 17. complete multiprotocol interface in eia530 mode applicatio s i for atio wu uu when the cable is removed, leaving all mode pins uncon- nected, the ltc2847/ltc2845 will enter no-cable mode. in this mode the ltc2847/ltc2845 supply current drops to less than 1000 m a and the ltc2847/ltc2845 driver outputs are forced into a high impedance state. at the same time, the r2 and r3 receivers of the ltc2847 are differentially terminated with 103 w and the other receiv- ers on the ltc2847 and ltc2845 are terminated with 30k w to ground. cable termination traditional implementations used expensive relays to switch resistors or required the user to change termina- tion modules every time a new interface standard was ltc2847 dce dte ltc2847 2847 f17 d3 r1 103 w 103 w 103 w r3 ltc2845 d3 d4 r4 d2 r1 r4 r2 r3 ll txc rxc rxd txd scte txc rxc rxd serial controller d2 103 w scte r2 d1 103 w txd r3 r1 d2 d1 ltc2845 d3 r2 r1 d1 r3 d2 d1 d4 txd scte txc rxc rxd rts dtr dcd dsr cts ll rts dtr dcd dsr cts rts dtr dcd dsr cts ll tm serial controller r2 d3 r5 d5 d5 r5 ri rl tm ri rl tm ri rl
12 ltc2847 sn2847 2847fs figure 18. single port dce v.35 mode selection in the cable figure 20. v.10 receiver input impedance figure 19. typical v.10 interface applicatio s i for atio wu uu selected. switching the terminations with fets is difficult because the fets must remain off when the signal voltage is beyond the supply voltage. alternatively, custom cables may contain termination in the cable head or route signals to various terminations on the board. the ltc2847/ltc2845 chip set solves the cable termina- tion switching problem by automatically providing the appropriate termination and switching on-chip for the v.10 (rs423), v.11 (rs422), v.28 (rs232) and v.35 electrical protocols. v.10 (rs423) interface all v.10 drivers and receivers necessary for the rs449, eia530, eia530-a, v.36 and x.21 protocols are imple- mented on the ltc2845. a typical v.10 unbalanced interface is shown in figure 19. a v.10 single-ended generator with output a and ground c is connected to a differential receiver with input a' con- nected to a, and ground c' connected via the signal return to ground c. usually, no cable termination is required for v.10 interfaces, but the receiver inputs must be compliant with the impedance curve shown in figure 20. the v.10 receiver configuration in the ltc2845 is shown in figure 21. in v.10 mode, switch s3 inside the ltc2845 is turned off. the noninverting input is disconnected inside the ltc2845 receivers and connected to ground. nc nc cable 2847 f18 ltc2847 ltc2845 connector (data) m0 m1 m2 dce/dte dce/dte m2 m1 m0 (data) aa ' cc ' generator balanced interconnecting cable load cable termination receiver 2847 f19 i z v z 10v ?.25ma 3.25ma ?v 3v 10v 2847 f20
13 ltc2847 sn2847 2847fs figure 22. typical v.11 interface figure 21. v.10 receiver configuration figure 24. typical v.28 interface figure 25. v.28 receiver configuration figure 23. v.11 receiver configuration 1 actually, there is no switch s1 in receivers r2 and r3. however, for simplicity, all termination networks on the ltc2847 can be treated identically if it is assumed that an s1 switch exists and is always closed on the r2 and r3 receivers. applicatio s i for atio wu uu the cable termination is then the 30k input impedance to ground of the ltc2845 v.10 receiver. v.11 (rs422) interface a typical v.11 balanced interface is shown in figure 22. a v.11 differential generator with outputs a and b and ground c is connected to a differential receiver with input a ' connected to a, input b ' connected to b, and ground c ' connected via the signal return to ground c. the v.11 interface has a differential termination at the receiver end that has a minimum value of 100 w . the termination resistor is optional in the v.11 specification, but for the high speed clock and data lines, the termination is essen- tial to prevent reflections from corrupting the data. the receiver inputs must also be compliant with the imped- ance curve shown in figure 20. in v.11 mode, all switches are off except s1 of the ltc2847s receivers which connects a 103 w differential termination impedance to the cable as shown in figure 23 1 . the ltc2845 only handles control signals, so no termination other than its v.11 receivers 30k input imped- ance is necessary. v.28 (rs232) interface a typical v.28 unbalanced interface is shown in figure 24. a v.28 single-ended generator with output a and ground c is connected to a single-ended receiver with input a ' connected to a and ground c ' connected via the signal return to ground c. r5 20k ltc2845 receiver 2847 f21 a b a ' b ' c ' r8 6k s3 r6 10k r7 10k gnd r4 20k aa ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 100 w min 2847 f22 r3 124 w r5 20k ltc2847 receiver 2847 f23 a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 aa ' cc ' generator balanced interconnecting cable load cable termination receiver 2847 f24 r3 124 w r5 20k ltc2847 receiver 2847 f25 a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1
14 ltc2847 sn2847 2847fs figure 28. charge pump figure 27. v.35 receiver configuration figure 26. typical v.35 interface applicatio s i for atio wu uu in v.28 mode, s3 is closed inside the ltc2847/ltc2845 which connects a 6k (r8) impedance to ground in parallel with 20k (r5) plus 10k (r6) for a combined impedance of 5k as shown in figure 25. proper termination is only pro- vided when the b input of the receivers is floating, since s1 of the ltc2847s r2 and r3 receivers remains on in v.28 mode 1 . the noninverting input is disconnected inside the ltc2847/ltc2845 receiver and connected to a ttl level reference voltage to give a 1.4v receiver trip point. v.35 interface a typical v.35 balanced interface is shown in figure 26. a v.35 differential generator with outputs a and b and ground c is connected to a differential receiver with input a ' connected to a, input b ' connected to b, and ground c ' connected via the signal return to ground c. the v.35 interface requires a t or delta network termination at the receiver end and the generator end. the receiver differen- tial impedance measured at the connector must be 100 w 10 w , and the impedance between shorted termi- nals (a ' and b ' ) and ground (c ') must be 150 w 15 w . a a ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 2847 f26 50 w 125 w 50 w 50 w 125 w 50 w r3 124 w r5 20k ltc2847 receiver 2847 f27 a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 in v.35 mode, both switches s1 and s2 inside the ltc2847 are on, connecting a t network impedance as shown in figure 27. the 30k input impedance of the receiver is placed in parallel with the t network termination, but does not affect the overall input impedance significantly. the generator differential impedance must be 50 w to 150 w and the impedance between shorted terminals (a and b) and ground (c) must be 150 w 15 w . no-cable mode the no-cable mode (m0 = m1 = m2 = 1) is intended for the case when the cable is disconnected from the con- nector. the charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the v cc supply current to the transceiver drops to less than 300 m a while its v in supply current drops to less than 10 m a. note that the ltc2847s r2 and r3 receivers continue to be terminated by a 103 w differential impedance. charge pump the ltc2847 uses an internal capacitive charge pump to generate v dd and v ee as shown in figure 28. a voltage doubler generates about 8v on v dd and a voltage inverter generates about C 7.5v on v ee . four 1 m f surface mounted tantalum or ceramic capacitors are required for c1, c2, c3 and c5. the v ee capacitor c4 should be a minimum of 3.3 m f. all capacitors are 16v and should be placed as close as possible to the ltc2847 to reduce emi. receiver fail-safe all ltc2847/ltc2845 receivers feature fail-safe opera- tion in all modes. if the receiver inputs are left floating or are shorted together by a termination resistor, the receiver output will always be forced to a logic high. 2847 f28 c3 1 f c5 1 f 5v c1 1 f c2 1 m f c4 3.3 m f ltc2847 v dd c1 + c1 v cc c2 + c2 v ee gnd +
15 ltc2847 sn2847 2847fs typical applicatio s u dte vs dce operation the dce/dte pin acts as an enable for driver 3/receiver 1 in the ltc2847, and driver 3/receiver 1 in the ltc2845. the ltc2847/ltc2845 can be configured for either dte or dce operation in one of two ways: a dedicated dte or dce port with a connector of appropriate gender or a port with one connector that can be configured for dte or dce operation by rerouting the signals to the ltc2847/ltc2845 using a dedicated dte cable or dedicated dce cable. a dedicated dte port using a db-25 male connector is shown in figure 29. the interface mode is selected by logic outputs from the controller or from jumpers to either v in or gnd on the mode select pins. a dedicated dce port using a db-25 female connector is shown in figure 30. a port with one db-25 connector, that can be configured for either dte or dce operation is shown in figure 31. the configuration requires separate cables for proper signal routing in dte or dce operation. for example, in dte mode, the txd signal is routed to pins 2 and 14 via the ltc2847s driver 1. in dce mode, driver 1 now routes the rxd signal to pins 2 and 14. power dissipation calculations the ltc2847 takes in 5v v cc . v dd and v ee are in turn produced from v cc with an internal charge pump at approximately 80% and 70% efficiency respectively. cur- rent drawn internally from v dd or v ee translates directly into a higher i cc . the ltc2847 dissipates power accord- ing to the equation: p diss(2847) = v cc ? i cc C n d ? p rt + n r ? p rt (1) p rt refers to the power dissipated by each driver in a receiver termination on the far end of the cable while n d is the number of drivers. conversely, current from the far end drivers dissipate power n r ? p rt in the internal receiver termination where n r is the number of receiv- ers. ltc2847 power dissipation consider an ltc2847 in x.21, dce mode (three v.11 drivers and two v.11 receivers). from the electrical char- acteristics table, i cc at no load = 14ma, i cc at full load = 100ma. each receiver termination is 100 w (r rt ) and current going into each receiver termination = (100ma C 14ma)/3 = 28.7ma (i rt ). p rt = (i rt ) 2 ? r rt (2) from equation (2), p rt = 82.4mw and from equation (1), dc power dissipation p diss(2847) = 5v ? 100ma C 3 ? 82.4mw + 2 ? 82.4mw = 418mw. consider the above example running at a baud rate of 10mbd. from the typical characteristic for v.11 mode i cc vs data rate, the i cc at 10mbd is 160ma. i cc increases with baud rate due to driver transient dissipa- tion. from equation (1), ac power dissipation p diss(2847) = 5v ? 160ma C3 ? 82.4mw + 2 ? 82.4mw = 718mw. ltc2845 power dissipation if a ltc2845 is used to form a complete dce port with the ltc2847, it will be running in the x.21 mode (three v.11 drivers and two v.10 drivers, two v.11 receivers and two v.10 receivers, all with internal 30k termination). in addi- tion to v cc , it uses the v dd and v ee outputs from the ltc2847. negligible power is dissipated in the large internal receiver termination of the ltc2845 so the n r ? p rt term of equation (1) can be omitted. thus equation (1) is modified as follows: p diss(2845) = (v cc ? i cc ) + (v dd ? i dd ) + (v ee ? i ee ) C n d ? p rt (3) since power is drawn from the supplies of the ltc2847 (v dd and v ee ) at less than 100% efficiency, the ltc2847 dissipates extra power to source p diss(2845) and p rt : p diss1(2847) = 125% ? (v dd ? i dd ) + 143% ? (4) (v ee ? i ee ) C p diss(2845) C n d ? p rt = 25% ? (v dd ? i dd ) + 43% ? (v ee ? i ee ) from the ltc2845 electrical characteristics table, for v cc = 5v, v dd = 8v and v ee = C 5.5v: i cc at no load 2.7ma i cc at full load with all drivers high 110ma i ee at no load 2ma i ee at full load with both v.10 drivers low 23ma i dd at no load 0.3ma i dd at full load 0.3ma
16 ltc2847 sn2847 2847fs figure 29. controller-selectable multiprotocol dte port with db-25 connector d2 d1 ltc2845 rts dtr dsr dcd cts d3 r2 r1 r4 r3 ltc2847 ll ri txd scte txc rxc rxd m0 m1 m2 dce/dte v cc v dd v ee gnd 2 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 18 * 7 16 c2 1 f c1 1 f c3 1 f c4 3.3 f 2847 f29 scte b rts a (105) rts b dtr a (108) dtr b cts a (106) cts b ll (141) ri (125) sg shield db-25 male connector dcd a (109) dcd b dsr a (107) dsr b d4 v cc 5v charge pump + v in d4enb r4en v in 3.3v v in 3.3v c9 1 f c7 1 f c8 1 f m0 m1 m2 dce/dte m0 m1 m2 d1 d2 d3 r1 r2 r3 txd a (103) txd b txc a (114) rxc a (115) rxd a (104) txc b rxc b rxd b scte a (113) r5 d5 c5 1 f c6 1 f t t t t t c10 1 f nc tm rl tm (142) rl (140) 25 21 *optional typical applicatio s u
17 ltc2847 sn2847 2847fs figure 30. controller-selectable dce port with db-25 connector typical applicatio s u d2 d1 ltc2845 cts dsr dtr dcd rts d3 r2 r1 r4 r3 ltc2847 ri ll rl tm rxd rxc txc scte txd m0 m1 m2 dce/dte v cc v dd v ee gnd 2 14 24 11 15 12 24 11 2 1 5 13 6 8 22 10 20 23 4 19 * 18 21 25 7 14 2847 f30 c2 1 f c1 1 f c3 1 f c4 3.3 f rxc b cts a (106) cts b dsr a (107) dsr b rts a (105) rts b sgnd (102) shield (101) db-25 female connector dcd a (109) dcd b dtr a (108) dtr b d4 v cc 5v charge pump + nc nc nc v in d4enb r4en v in 3.3v c9 1 f c7 1 f c8 1 f m0 m1 m2 dce/dte m0 m1 m2 d1 d2 d3 r1 r2 r3 rxd a (104) rxd b scte a (113) txd a (103) txc b scte b txd b rxc a (115) c5 1 f c6 1 f t t t t t c10 1 f v in 3.3v txc a (114) *optional r5 d5 ri (125) ll (141) rl (140) tm 9142)
18 ltc2847 sn2847 2847fs figure 31. controller-selectable multiprotocol dte/dce port with db-25 connector typical applicatio s u d2 d1 ltc2845 d3 r2 r1 r4 r3 ltc2847 m0 m1 m2 dce/dte v cc v dd v ee gnd 2847 f31 c2 1 f c1 1 f c3 1 f c4 3.3 f d4 d5 v cc 5v charge pump + dce/dte v in d4enb r4en 15 v in 3.3v c9 1 f c7 1 f c8 1 f m0 m1 m2 dce/dte m0 m1 m2 d1 d2 d3 r1 r2 r3 c5 1 f c6 1 f t t t t t c10 1 f dte_txd/dce_rxd dte_scte/dce_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_ll/dce_ri dte_ri/dce_ll dte_tm/dce_rl dte_rl/dce_tm 2 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 18 * 25 21 7 16 scte b rts a rts b dtr a dtr b cts a cts b dsr a dsr b cts a cts b sg shield db-25 connector dcd a dcd b dsr a dsr b rts a rts b dcd a dcd b dtr a dtr b txd a txd b txc a rxc a rxd a txc b rxc b rxd b txc a scte a txd a txc b scte b txd b scte a rxc b rxd a dte dce rxd b rxc a v in 3.3v r5 ll ri tm rl ll ri tm rl *optional nc
19 ltc2847 sn2847 2847fs information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio 5.00 0.10 (2 sides) note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 0.40 0.10 37 1 2 38 bottom view?xposed pad 5.15 0.10 (2 sides) 7.00 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0303 0.50 bsc 0.200 ref 0.200 ref 0.00 ?0.05 recommended solder pad layout 3.15 0.10 (2 sides) 0.18 0.18 0.23 0.435 0.00 ?0.05 0.75 0.05 0.70 0.05 0.50 bsc 5.20 0.05 (2 sides) 3.20 0.05 (2 sides) 4.10 0.05 (2 sides) 5.50 0.05 (2 sides) 6.10 0.05 (2 sides) 7.50 0.05 (2 sides) 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701)
20 ltc2847 sn2847 2847fs lt/tp 0603 1k ? printed in usa ? linear technology corporation 2003 related parts part number description comments ltc1321 dual rs232/rs485 transceiver two rs232 driver/receiver pairs or two rs485 driver/receiver pairs ltc1334 single 5v rs232/rs485 multiprotocol transceiver two rs232 driver/receiver or four rs232 driver/receiver pairs ltc1343 software-selectable multiprotocol transceiver 4-driver/4-receiver for data and clock signals ltc1344a software-selectable cable terminator perfect for terminating the ltc1543 (not needed with ltc1546) ltc1345 single supply v.35 transceiver 3-driver/3-receiver for data and clock signals ltc1346a dual supply v.35 transceiver 3-driver/3-receiver for data and clock signals ltc1543 software-selectable multiprotocol transceiver terminated with ltc1344a for data and clock signals, companion to ltc1544 or ltc1545 for control signals ltc1544 software-selectable multiprotocol transceiver companion to ltc1546 or ltc1543 for control signals including ll ltc1545 software-selectable multiprotocol transceiver 5-driver/5-receiver companion to ltc1546 or ltc1543 for control signals including ll, tm and rl ltc1546 software-selectable multiprotocol transceiver 3-driver/3-receiver with termination for data and clock signals ltc2844 3.3v software-selectable multiprotocol transceiver companion to ltc2846 for control signals including ll ltc2845 3.3v software-selectable multiprotocol transceiver 5-driver/5-receiver companion to ltc2846 or ltc2847 for control signals including ll, tm and rl ltc2846 3.3v software-selectable multiprotocol transceiver 3.3v supply, 3-driver/3-receiver with termination for data and clock signals, generates the required 5v and 8v supplies for ltc2846 companion parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com the v.11 drivers are driven between v cc and gnd while the v.10 drivers are driven between v cc and v ee . assume that the v.11 driver outputs are high and v.10 driver outputs low. current going into each 100 w v.11 receiver termination = (110ma C 2.7ma) C 23ma/3 = 28.1ma. current going into each 450 w v.10 receiver termination = 23ma C 2ma/2 = 10.5ma. from equation (2), v.11 p rt = 79mw and v.10 p rt = 49.6mw. from equation (3), p diss(2845) = 5v ? (110ma C 23ma) + (8v ? 0.3ma) + 5.5v ? 23ma C 3 ? 79mw C 2 ? 49.6mw = typical applicatio s u 228mw. since the ltc2845 runs slow control signals, the ac power dissipation can be assumed to be equal to the dc power dissipation. the extra power dissipated in the ltc2847 due to ltc2845 is given by equation(4), p diss1(2847) = 25% ? (8v ? 0.3ma) + 43% ? (5.5v ? 23ma) = 55mw. so for an x.21 dce port running at 10mbd, the ltc2847 dissipates approximately 718mw + 55mw = 773mw while the ltc2845 dissipates 228mw.

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